Using LISATek for the Design of an ASIP Core including Floating Point Operations

Application specific instruction set processors (ASIPs) recently became more important to overcome compute bottlenecks in digital signal processing systems with tight power constraints. Within the last years commercial tools like the LISATek framework came up, that allow to design ASIP architectures by using their own description language. It shortens the design cycle dramatically compared to classical register-transfer-level (RTL) based approaches. However, if such designed ASIPs are used in complex system-on-chip designs, they must easily integrate into existing design flows to allow an iterative design process. In this paper we investigate the capabilities of the LISATek framework by implementing a RISC core compliant to the SH-1. Additionally we integrated existing IP cores in terms of a floating point processing unit into the architecture to enable instruction customization. Thereby we observed some minor limitations, which have to be overcome in future for a better practical design flow. Index Terms ASIP, RISC, LISA, floating point, architecture exploration